1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor device.
2. Description of the Related Art
In general, a semiconductor device such as DRAM (Dynamic Random Access Memory) includes a plurality of banks that transmit and receive data through a global I/O line.
FIG. 1 is a block diagram of a conventional semiconductor device.
Referring to FIG. 1, the semiconductor device 10 includes first to fourth banks 11A to 11D arranged in parallel at a certain distance from each other in an upper region, fifth to eighth banks 11E to 11H arranged in a lower region so as to oppositely face the first to fourth banks 11A to 11D, respectively, an I/O circuit 13 configured to transfer data between the first to eighth banks 11A to 11H and an external device, and a global I/O line GIO configured to electrically connect the first to eighth banks 11A to 11H with the I/O circuit 13.
In the semiconductor device 10 having the above-described configuration, distances from the I/O circuit 13 to the first to eighth banks 11A to 11H are different, respectively. That is, the lengths of the global I/O line GIO are different for different banks, respectively. Therefore, data skew may occur according to different line loading conditions. For example, as illustrated in FIG. 1, since a distance between the I/O circuit 13 and the first bank 11A (path A) is different from a distance between the I/O circuit 13 and the second bank 11B (path B), data skew occurs according to differences in the paths.
FIG. 2 is a block diagram of another conventional semiconductor device.
Referring to FIG. 2, the semiconductor device 20 includes first to fourth banks 21A to 21D arranged in parallel at a certain distance from each other in an upper region, fifth to eighth banks 21E to 21H arranged in a lower region so as to oppositely face the first to fourth banks 21A to 21D, respectively, an I/O circuit 23 configured to transfer data between the first to eighth banks 21A to 21H and an external device, a first global I/O line GIO01 configured to electrically connect the I/O circuit 23 with the banks 21A, 21B, 21E, and 21F, which are arranged in the left side among the first to eighth banks 21A to 21H, and a second global I/O line GIO02 configured to electrically connect the I/O circuit 23 with the bands 21C, 21D, 21G, and 21H, which are arranged in the right side among the first to eighth banks 21A to 21H.
The semiconductor device 20 having the above-described configuration may correct data skew to some extent through the global I/O lines GIO01 and GIO02 when compared to the semiconductor device 10 illustrated in FIG. 1. However, data skew still occurs according to a path characteristic between different paths, for example, ‘path A’ and ‘path B’, of each global I/O line.
Thus, different techniques have been developed to address the above features of the above-described semiconductor devices 10 and 20. For example, Korean Patent Laid-Open Publication No. 1999-0013926 (hereinafter, referred to as “Prior Art 1”) discloses a technique for equalizing signal delay times using a plurality of data paths, and Korean Patent No. 10-0780633 (hereafter, referred to as “Prior Art 2”) discloses a technique for reducing skew depending on the distance using a plurality of delay circuits. However, since Prior Art 1 Includes the plurality of data paths and Prior Art 2 includes the plurality of delay circuits, they increase the circuit area.